Fabrication · Physics · Supply Chain
From sand to compute.
Under every program is a slice of purified rock with billions of microscopic switches carved into it, flipped on and off by voltage. This is the full pipeline from sand to working chip: the intuition, the physics, the math, and the real path to building it yourself.
01 / The mental model
A chip is a billion switches you printed with light
Before any process makes sense, you need the right abstraction: a modern chip is an enormous lattice of voltage-controlled switches (transistors), wired into logic. The entire job of a fab is to print those switches and wires, layer by layer, onto silicon.
The transistor = a faucet for electrons
The MOSFET has three terminals: source, drain, and gate. Current wants to flow source→drain, but an insulated gate sits in the middle like a valve. Enough voltage on the gate pulls a conductive channel into existence: the faucet opens, electrons flow, the switch is ON (1). Drop the voltage and the channel vanishes, leaving it OFF (0).
The gate doesn't touch the current; it controls it through a thin insulator, purely by electric field. That insulator is why "gate oxide" is one of the most obsessed-over layers in the whole process.
Why silicon, and what "doping" really does
Metals always conduct; glass never does. Silicon is a semiconductor, in between, and controllable, which is the whole point. Pure silicon barely conducts. You change it by doping: mixing in trace impurities. n-type (phosphorus) donates spare electrons; p-type (boron) creates "holes."
The abstraction stack: from software down to switches
This is the map for the whole guide. Fabrication builds the bottom layers physically; everything above the transistor is software, everything below it is physics.
The rest of this guide walks L1 → L2: the physical manufacture of switches and wiring.
02 / Sand → wafer
Making a flawless canvas out of rock
You can't print circuits on dirty, lumpy material. Step one of any fab is producing a single crystal of silicon, 99.9999999% pure (nine nines), sliced into mirror-flat discs called wafers. Every later step happens on top of this.
Czochralski growth: pulling a perfect crystal
Molten silicon is held just above melting. A tiny seed crystal touches the surface and is slowly rotated and pulled upward. Atoms latch onto the seed's lattice in perfect alignment, so the whole boule (often 2 m long, 300 mm across) is one continuous crystal with no grain boundaries.
03 / Photolithography
The printing press at the heart of everything
Lithography turns a circuit drawing into a physical pattern. It's the single most important (and most repeated) step. A leading chip runs this loop 50 to 100 times, once per layer. Master this and you understand the fab.
mask = the source pattern (the layout file)
light = projects that pattern onto the wafer
resist = the coating the pattern develops into
etch = removes material through the openings
# then run the whole sequence again for the next layer:
# each layer stacks on the one below it, so the chip
# is built up physically, layer over layer.
A side-view cross-section of the wafer surface. Step through the loop.
Resist: the light-sensitive paint
The wafer is spin-coated with photoresist, a polymer whose chemistry changes where light hits it. Positive resist becomes soluble where exposed (the lit pattern washes away); negative does the opposite. After developing, you're left with a stencil protecting some areas and exposing others.
The stepper: a reduction camera
The exposure tool shines light through the mask, then through a lens that shrinks the image 4× onto the wafer, and "steps" across to repeat it per die. Reduction is a gift: a mask with 4×-larger features is far easier to make. The lens does the hard part.
04 / Resolution & EUV
The math of small, and the machine that prints it
How tiny can you print? It comes down to one equation from optics. Understanding it explains the entire 40-year race down to today's nodes, and why a single Dutch company controls the future.
CD = k₁ · λ / NA
λ = wavelength of light
NA = numerical aperture (how wide the lens grabs light)
k₁ = process cleverness factor (theoretical floor ≈ 0.25)
# to print smaller: shrink λ, raise NA, or lower k₁.
# the whole industry is a 40-year war on these 3 numbers.
Tap a preset to jump to a real technology generation, or drag the sliders. Watch how many lines you can pack into the same width.
Why EUV is borderline impossible
To get 13.5 nm light you can't use a normal lamp or laser. Here's what ASML's machines actually do, 50,000 times per second:
One droplet-to-light cycle, slowed roughly a million times. Play the loop or step it phase by phase. In a real machine this whole sequence repeats 50,000 times every second, a fresh tin droplet vaporized every 20 microseconds.
Vaporize tin
A droplet of molten tin is shot through a vacuum. A laser pre-pulse flattens it into a pancake.
Blast it twice
A massive CO₂ laser hits the flattened droplet, making a ~500,000 °C plasma that emits 13.5 nm light.
Mirrors, never lenses
EUV is absorbed by everything: glass, air, your hand. Optics are ultra-smooth Mo/Si multilayer mirrors, all in vacuum.
Collect the scraps
Only a few percent of light survives to the wafer. The machine weighs ~180 tons, costs ~$200M, ships in 40+ crates.
When you can't shrink λ: multi-patterning & high-NA
From 2007–2018 the industry was stuck at 193 nm yet kept shrinking, via multi-patterning: split one dense pattern into 2–4 masks/exposures that interleave on the wafer (expensive, like rendering one frame in multiple passes). EUV collapsed many passes back into one. Next up: High-NA EUV (NA 0.55), rolling out now.
05 / Deposit · etch · dope
Adding, removing, and re-flavoring material
Lithography only makes the stencil. Three families of process actually change the wafer: deposition adds material, etching removes it, and doping changes the silicon's electrical personality.
Deposition: thin films, sometimes one atom at a time
| Method | How | Analogy |
|---|---|---|
| CVD | Gases react and deposit a solid film | Spray-paint a coat |
| PVD | Sputter/evaporate metal atoms onto the surface | Vapor-blast a layer on |
| ALD | One atomic layer per cycle, self-limiting | One exact layer at a time |
| Epitaxy | Grow new crystal aligned to the wafer below | Extend the existing structure |
self-limiting: each cycle deposits exactly one molecular layer and then stops, no matter how long you wait. That is the only way to build the angstrom-thin, perfectly uniform gate insulators modern transistors need.
Four self-limiting sub-steps make one cycle. Precursor A saturates every open surface site and then stops (extra molecules bounce off, that is what "self-limiting" means). Purge, then co-reactant B converts that layer into film and frees the sites again. Play it or step through, and watch the film grow exactly one layer per cycle.
Etching: anisotropic is everything
Wet etching dunks the wafer in chemicals: fast, but eats sideways too (isotropic), blurring features. Dry / plasma etching fires energized ions straight down, carving sharp vertical walls. At nanometer scale you need walls, not slopes.
Doping: the random walk hiding inside Fick's law
To make n-type or p-type regions, drive dopant atoms into the silicon. Ion implantation literally accelerates dopant ions in a particle accelerator and fires them into the wafer; a high-temperature anneal repairs the lattice and lets atoms settle. How they spread is pure statistics.
# Each dopant does a random walk: hop up/down/left/right, no memory.
# Aggregate millions of walkers → a smooth bell-shaped profile emerges.
∂C/∂t = D · ∂²C/∂x²
# that's the entire content of the diffusion equation.
Every dot is one dopant atom doing a random walk into the silicon. The bars on the right are the concentration-vs-depth profile building up in real time: Fick's law happening atom by atom.
CMP: polish flat, then do it all again
After stacking layers, the surface gets bumpy. Chemical-Mechanical Planarization grinds it back to a mirror flat, because the next lithography step needs a level surface to stay in focus (recall the tiny depth-of-field at 13.5 nm).
06 / Transistors & wiring
Build the switches first, then wire the city
A fab's flow splits in two. FEOL (front-end-of-line) builds the transistors in the silicon. BEOL (back-end-of-line) builds the 10–15+ stacked layers of copper wiring connecting billions of them: a microscopic multi-level highway system.
Front-end-of-line
Wells, gates, gate oxide, source/drain doping. Where the actual transistors form. Highest precision, smallest features.
Back-end-of-line
Copper "damascene" interconnect in many stacked layers, separated by low-k insulator, joined by vertical vias. Lower layers dense and fine; upper layers fat power/clock rails.
Transistor evolution: chasing control of the channel
As transistors shrank, the flat gate lost grip and current leaked even when "off" (wasted power, heat). The fix each generation: wrap the gate around more of the channel.
Looking down the channel (source→drain runs into the screen). Toggle the generation: watch the orange gate wrap around more of the blue channel, and the off-state leakage current bleeding through drop as electrostatic control tightens.
Copper interconnect: the damascene trick
Copper is hard to etch, so wiring is built in reverse: etch trenches in the insulator, fill with copper, then CMP away the excess so only wires-in-trenches remain. Named after the inlay metalwork of Damascus. Repeat per metal layer.
07 / Test & package
Sort the survivors, then armor them
A finished wafer is a grid of identical dies, but they aren't all equal; defects are scattered randomly. The back end is about finding the good ones, cutting them out, and connecting them to the world.
Probe, then bin
Before dicing, every die is electrically tested on the wafer ("wafer probe"). Working dies are binned by speed and power efficiency.
A/B sorting at the hardware level. The same design comes off the line at a spread of qualities. Best-clocking dies become the premium part; weaker ones sell at lower clocks; partly-defective ones may have a bad core disabled and ship cheaper. One wafer → a whole product ladder.
Dice, package, bond
The wafer is sawn or laser-cut into individual dies. Each good die is mounted in a package that protects it and fans its microscopic pads out to pins/balls you can solder to a board.
Advanced packaging: where the action moved
With single-chip shrinking getting brutal, gains now come from combining chips: chiplets, 3D stacking, silicon interposers (TSMC's CoWoS), and stacked memory (HBM). Modern AI accelerators are really several dies fused into one package.
# a defect kills a whole die, so smaller dies waste
# less silicon per defect. Four small dies survive
# defects far better than one big one, and you can
# even mix process nodes. Economics force the packaging.
Same total logic, two ways to build it. Toggle between one big monolithic die and four chiplets sitting on a silicon interposer next to HBM memory stacks. Drag the die size up and watch the yield gap explode: the chiplet approach uses the exact same e^(−A·D) model from §08, just on four small dies instead of one giant one.
08 / Yield & economics
The equation behind chip economics
Defects are random and unavoidable. The fraction of working dies is the yield, and it dictates cost, chip size, and why chiplets exist. It's also simple enough to write in five lines of code.
# chance a die of area A catches ZERO defects:
Yield = e^(−A·D)
# double the die area → yield falls off a cliff, exponentially.
Random red defects scatter on a 300 mm wafer. Any die containing a defect dies (dark). Shrink the die or clean up the process and watch yield climb.
Why a fab costs more than an aircraft carrier
$10B–$20B+
One leading-edge fab. EUV tools alone run ~$200M each, and you need dozens.
Class 1 cleanroom
Air ~10,000× cleaner than a hospital OR. A single dust speck destroys a die.
~3 leading-edge players
Only TSMC, Samsung, and Intel do the bleeding edge. The cost barrier created a near-monopoly.
Yield ramps for years
New nodes launch at low yield and improve through relentless defect-hunting. Early yield is the moat.
09 / The supply chain
No single country can build a chip alone
A finished phone chip might be designed in California on British IP, using American software, printed in Taiwan on a Dutch machine, with Japanese chemicals and German optics. The supply chain is a globe-spanning relay with brutal chokepoints.
Three business models, one ecosystem
| Model | Does what | Examples |
|---|---|---|
| Fabless | Designs chips, owns no factory | Nvidia, Apple, AMD, Qualcomm |
| Foundry | Manufactures others' designs | TSMC, GlobalFoundries |
| IDM | Designs and manufactures | Intel, Samsung, Micron |
10 / The build path
What "from scratch" actually means for you
Honest truth: you can't build a leading-edge chip in a garage: that needs ~$20B and a Dutch monopoly's blessing. But "0 → hero" is real, and there are three legitimate ladders you can start climbing this week, in order of accessibility.
Design & tape out a real chip
Write hardware in Verilog / Chisel, target the open SkyWater SKY130 PDK, run the open OpenLane / OpenROAD flow (synth → place → route → GDSII), and submit to a shared shuttle like Tiny Tapeout to get a physical chip back in the mail. You'll touch every concept here as a real tool, not a metaphor.
Model every step in code
The nine simulators in this guide are runnable models: extend them. Build the Rayleigh tool, a Monte-Carlo diffuser, a Poisson yield estimator, a logic-gate sim from MOSFET equations. This is where a software brain has a genuine edge.
Make transistors at home
Sam Zeloof built working ICs in a home lab (~1960s–70s nodes); Jeri Ellsworth made hand-built transistors. Not nanometers, but real lithography, etching, and doping at micron-ish scale with serious safety discipline. Proof the whole loop is comprehensible by one person.
The prerequisites
Digital logic & boolean algebra → a little semiconductor physics (band gap, P-N junction, MOSFET I–V) → an HDL → the open EDA flow. Each maps onto a section above: §01 logic, §05 physics, §06 devices, §10 tooling.